1) What is cache? Explain the difference between direct-mapped and N-way associative cache. What are the advantages and disadvantages of each?
2) What is DMA? (direct memory access). What are its uses and why is it good? (saves CPU time, etc).
3) Make a float-to-char converter (convert a float into a string of chars, representing each digit of the float). Some points to consider:
- Data type choice…long vs. int vs. float.
- When using the divide and shift method, be careful of division by 0 error when the input is 0.
- Need two for-loops for divide-and-shift method to handle decimals.
4) A thread is operating on a circular buffer with “head” and “tail” pointers using methods:
– int getData()
– void putData(int)
describe the operations.
5) Now there are two threads operating on the above circular buffer with the same available methods. How to solve contention?
6) Make a method: bool doesProdExist(int* a, int* b, int* c, int value, int n)
-a, b, and c are n-lengthed integer arrays
The method returns if we can take a number from each of a, b, and c whose product is equal to “value”.
- Naive brute-force method: O(n^3).
- Go through one array, save the quotient of “value” and each number in that array: O(n),
- Perform the same operation on the second array, storing the quotient between every number of the first quotient array and every number of the second array: total=O(n^2) so far.
- Do a binary search of the numbers from the second quotient array in the third array: total=O(n^2*Log(n)).
- Special case: value=0.
My big-O is prob not entirely correct…
7) Memory controller (MC) testing design. The MC is a 8-entry, 32-bits register bank. Has inputs: addr, WE, CLK, reset_n, outputs, and BE. BE=Byte Enable, which allows for writing specific bytes to a register entry.
Corner case: test if the address wirings are correct by using pre-populated register files.
8) DP (dual-port) memory testing design. The DP is a 13-entry, 8-bits register bank. Has inputs: addr_in, addr_out, data_in, data_out, WE, clk, reset_n, and error. Some things of note:
- A dual-port memory allows for independent writing and reading. Need to make sure that the same data is not written and read at the same time by gating addr_in, addr_out, and WE lines.
- There’s a total of 13 entries, that means certain addr values are not mapped to an entry. Need to do error-handling…read_error and write_error.
- Correct synthesis using full case statement/conditionals to avoid extra latches.
9) Describe t_setup and t_hold. In hardware, how to debug for timing problems?
– Vary supply voltage and temperature to change logic propagation delay.
– Change clock speed to diagnose t_setup time problems.
10) FIFO buffer testing design.
– Circular buffer with header and tail pointers.
– Full and empty conditions.
– Use gray-coding for different-clock domain access of the same buffer.